Modern integrated circuits (“ICs”) in production contain ever-increasing numbers of components. Testing of those ICs requires a large number of test patterns. For each IC to be tested, design for test (“DFT”) designers have the challenge of inputting a huge volume of scan test sequences, produced by techniques such as automatic test pattern generation (“ATPG”), via a minimal number of test pins, with consequent substantial test time and tester memory requirements.
In order to address these challenges, DFT designers have used a technique called Test Compression. Test Compression reduces test data volume and test application time (“TAT”) while retaining test coverage. Using Test Compression, highly compressed test stimuli can be applied to low-pin count automated test equipment (“ATE”), which decompresses the test stimuli stored on the ATE to the actual test stimuli to be applied to a large number of scan channels that feed the logic under test. After applying the scan chain data to the logic under test one or more functional clocks are applied and the test stimuli is captured by the scan channels and the test stimuli is then compressed for measurement and comparison. Test Compression recognizes that only a small percentage of scan cells in an ATPG-generated scan chain (“care bits”) are necessary for testing. Test Compression modifies the design to apply the care bits in shorter scan chains, reducing the TAT. The compression ratio generated by Test Compression methods is capable of greatly reducing the test data volume and TAT. For example original data having a volume of 6 Gb and TAT of 20 seconds is, at a 100× compression ratio, reduced by 99% to 60 Mb and TAT of 0.2 seconds.
Test Compression is driven by two structures: a Decompressor and a Compressor (or Compactor). The Decompressor drives the compressed test stimuli onto the IC from the small number of scan-in pins on the ATE to the large number of internal scan channels which feed the logic under test. The Decompressor is designed to allow a continuous flow of stimuli so that it is possible to load the scan chain data for a given test onto the IC and to unload from the IC the previous test response data to the Compressor, all in a single clock cycle. Compression and Decompression logic generally are built using discrete logic gates such as XORs, multiplexers and flip-flops and placed inside a logic module called CoDec which is normally placed in one corner of the IC. Wires transfer test stimuli from the DeCompressor inside the CoDec to the head of the scan channels which may be distributed across the area of the IC. Similarly wires from the tails of the scan channels transfer the test stimuli to the Compressor inside the CoDec.
Wiring all of these connections directly between the scan chains scattered over the surface area of the IC and the decompression and compression logic is referred to as traditional global scan wiring. To reduce the cost of testing ICs DFT engineers try to build more scan chains of a shorter length to increase the compression ratio. Higher compression ratios mean that there are more wires running from the CoDec to the heads and tails of the shorter and more numerous scan chains, The additional wiring increases the footprint of the IC and may lead to wiring congestion in some areas of the IC. Several methods have been introduced in efforts to correct the on-board congestion issues associated with compression logic, such as improved XOR mapping and partitioned Compressor-Decompressors. However, these methods are at best incremental improvements and do not address the issue of area overhead and extreme wiring congestion.
As chip complexity increases, compression ratios have to increase. However, the physical chip layout can prevent implementation of the large compression ratios needed to reduce the cost of test. At a certain point, the total number of wires that can be manufactured and connected to the CoDec presents a bottleneck.